The present invention relates generally to integrated circuit testing techniques and, more particularly, to an apparatus and method for selectively implementing launch-off-scan capability in at-speed testing of integrated circuit devices.
The testing of integrated circuits has evolved into a highly developed area of technology. Generally, such testing may be implemented through the use of external equipment, Built-In Self-Test (BIST) circuitry, or a combination of the two. Typically, all test methodologies involve shifting data into scannable memory elements of an integrated circuit device (e.g., Level Sensitive Scan Design or LSSD latches), capturing the input to the memory elements, shifting the captured data out and then comparing the captured data with predetermined values to determine whether the circuit has performed according to design. Automatic test pattern generation (ATPG) systems use tools for testing digital circuits after the circuits have been manufactured. In general, an ATPG tool generates a set of test vectors that are applied to a circuit under test. The output of the circuit is analyzed to identify logic faults in the circuit design (i.e., “functional testing”), as well as detecting fabrication defects (i.e., “structural testing”).
“At-speed” testing refers to testing techniques to detect defects that are only apparent when the circuit is running at system speed. Many time-based defects cannot be detected unless the circuit is run at-speed. Examples of time related defects that occur at-speed include high impedance shorts, in-line resistance, and cross talk between signals. There are two general approaches to performing at-speed testing of combinational logic and latches in response to a test pattern that has been scanned-in, followed by a scan-out of the test results: Launch-off-Capture (LoC) and Launch-off-Scan (LoS).
LoC may be used in conjunction with any edge-based style of flip-flops or “flops,” wherein the system (edge) clock is controlled at the root (e.g., source) of the clock. LoC permits a number (typically 2) of pulses to enter the clock fanout, thus the result of two clock pulses at the flops is a two-cycle execution of system operation. The two cycles may be described as the transitions between three states: present state/launch state/capture state. Although two cycles of system operation are executed, only the second cycle (i.e., the launch state to capture state transition) is actually an at-speed test. While the test clock is steady-state low prior to the first clock pulse, the master latch portion of each flop has already captured a combinational value (i.e., the launch state) because, as a flop function, the master latch loads or “captures” data while the edge clock is low, and the slave latch loads or “launches” data while the clock is high.
On the other hand, the “first pulse to second pulse” (i.e., the second cycle) is a cycle that executed at-speed since the slave latch launches into the combinational logic and the result (capture state) is loaded into the flops (into the master between the two pulses, and into the slave upon the second pulse) to complete the test. Although the final clock test state is low (meaning that an additional state has now been loaded into the master latches), the subsequent scan out of the flop will result in a shift out of the resulting capture state in the slave latch.
LoC is a simple technique; however, since it requires two cycles of system state transition, it results in less efficient test patterns than with respect to a one-cycle or simple combinational test. More specifically, it is less efficient because the capture state of each flop depends upon the value in its driving flops in the launch state, and each of these driving flops depends in turn on its own driving flops from the present state. This exponential increase in flop dependency thus reduces the number of parallel at-speed tests that can be contained in a single scanned pattern. Experimentally, this has been seen as a 6× increase over test patterns whose test operates a one-cycle execution of system operation.
In contrast, conventional LoS operates only in conjunction with certain types of edge-based flops. As is the case with LoC, two test clock pulses are issued in LoS. However, during the first clock pulse in LoS, a “Scan Enable” signal is held high such that the scanned pattern will shift for one additional cycle after the original pattern scan load. As a result, the initially scanned value in the master and slave latches is both the present and launch states. After the first pulse but before the second pulse, the Scan Enable signal is deactivated (set to 0) such that the second pulse will result in the capture of the next system state (capture state) into both the master and slave latches. Therefore, only one cycle of system state has been executed. Subsequently, the test results are shifted out, similar to LoC.
One problem with conventional LoS is that both the Scan Enable signal and the scan chain itself are subject to timing hazards, thus requiring timing closure devices (e.g., lock-up latches) across clock domain boundaries added to the design. Alternatively, the test clock may be configured to be free running, as opposed to generating two clock pulses. A clock splitter is also enhanced so as to include two gates, one for each of the master and slave clocks. As a result, the scanned-in sequence is a “skewed load” in that for the final cycle of “master (A)-slave (B)” scan clocking, only a master (A) scan clock is issued. This leaves the scanned pattern (present and launch state) in the master latches. However, the clock splitter gating keeps both the master and slave clocks low, until a synchronous transition of a control signal is received simultaneously by all clock splitters, at which time the slave clock will be ungated for a cycle (allowing launch from slave), the master clock is ungated ½ cycle later (allowing capture in master). Finally, the slave clock remains ungated ½ cycle later (allowing the master's captured data to be loaded into the slave). After this sequence, the slave latches contain the capture state, followed by a scan out of the result.
Although this modified LoS approach is an advantage over the previous LoS technique with respect to avoiding timing hazards in the scan chain (or the need to add timing closure devices in the scan chain), there is still a global timing requirement on the synchronous control signal.
Accordingly, it would be desirable to be able to address the shortcomings of conventional LoS, but in a manner that avoids both timing hazards in the scan chain, as well as the need for a global timing requirement on the synchronous control signal.